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TMS320VC5501PGF300 Dip Ic Sockets Ic Fxd-Pnt Dsp 600 Mips 176-Lqfp
Product Details:
| Place of Origin: | original |
| Brand Name: | original |
| Certification: | original |
| Model Number: | TMS320VC5501PGF300 |
Payment & Shipping Terms:
| Minimum Order Quantity: | 1 |
|---|---|
| Price: | negotiation |
| Packaging Details: | carton box |
| Delivery Time: | 1-3working days |
| Payment Terms: | T/T, L/C |
| Supply Ability: | 100,000 |
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Detail Information |
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| Mfr: | Texas Instruments | Series: | TMS320C55x |
|---|---|---|---|
| Package: | Tray | Product Status: | Active |
| Type: | Fixed Point | Interface: | Host Interface, I²C, McBSP, UART |
| Non-Volatile Memory: | 300MHz | Mfr Texas Instruments Series TMS320C55x Package Tray Product Status Active Type Fixed Point Interfac: | ROM (32kB) |
Product Description
TMS320VC5501PGF300 Dip Ic Sockets Ic Fxd-Pnt Dsp 600 Mips 176-Lqfp
IC FXD-PNT DSP 600 MIPS 176-LQFP
Specifications of TMS320VC5501PGF300
| TYPE | DESCRIPTION |
| Category | Integrated Circuits (ICs) |
| Embedded | |
| DSP (Digital Signal Processors) | |
| Mfr | Texas Instruments |
| Series | TMS320C55x |
| Package | Tray |
| Product Status | Active |
| Type | Fixed Point |
| Interface | Host Interface, I²C, McBSP, UART |
| Clock Rate | 300MHz |
| Non-Volatile Memory | ROM (32kB) |
| On-Chip RAM | 48kB |
| Voltage - I/O | 3.30V |
| Voltage - Core | 1.26V |
| Operating Temperature | -40°C ~ 85°C (TC) |
| Mounting Type | Surface Mount |
| Package / Case | 176-LQFP |
| Supplier Device Package | 176-LQFP (24x24) |
| Base Product Number | TMS320 |
Features of TMS320VC5501PGF300
• High-Performance, Low-Power, Fixed-Point TMS320C55x Digital Signal Processor (DSP)
− 3.33-ns Instruction Cycle Time for 300-MHz Clock Rate
− 16K-Byte Instruction Cache (I-Cache)
− One/Two Instructions Executed per Cycle
− Dual Multipliers [Up to 600 Million Multiply-Accumulates Per Second (MMACS)]
− Two Arithmetic/Logic Units (ALUs)
− One Program Bus, Three Internal Data/Operand Read Buses, and Two Internal Data/Operand Write Buses
• Instruction Cache (16K Bytes)
• 16K x 16-Bit On-Chip RAM That is Composed of Four Blocks of 4K × 16-Bit Dual-Access RAM (DARAM) (32K Bytes)
• 16K × 16-Bit One-Wait-State On-Chip ROM (32K Bytes)
• 8M × 16-Bit Maximum Addressable External Memory Space
• 32-Bit External Parallel Bus Memory Supporting External Memory Interface (EMIF) With General-Purpose Input/Output (GPIO) Capabilities and Glueless Interface to:
− Asynchronous Static RAM (SRAM)
− Asynchronous EPROM
− Synchronous DRAM (SDRAM)
− Synchronous Burst RAM (SBRAM)
• Emulation/Debug Trace Capability Saves Last 16 Program Counter (PC) Discontinuities and Last 32 PC Values
• Programmable Low-Power Control of Six Device Functional Domains
• On-Chip Peripherals
− Six-Channel Direct Memory Access (DMA) Controller
− Two Multichannel Buffered Serial Ports (McBSPs)
− Programmable Analog Phase-Locked Loop (APLL) Clock Generator
− General-Purpose I/O (GPIO) Pins and a Dedicated Output Pin (XF)
− 8-Bit Parallel Host-Port Interface (HPI)
− Four Timers
− Two 64-Bit General-Purpose Timers
− 64-Bit Programmable Watchdog Timer
− 64-Bit DSP/BIOS Counter
− Inter-Integrated Circuit (I2C) Interface
− Universal Asynchronous Receiver/ Transmitter (UART)
• On-Chip Scan-Based Emulation Logic
• IEEE Std 1149.1† (JTAG) Boundary Scan Logic
• Packages:
− 176-Terminal LQFP (Low-Profile Quad Flatpack) (PGF Suffix)
− 201-Terminal MicroStar BGA (Ball Grid Array) (GZZ and ZZZ Suffixes)
• 3.3-V I/O Supply Voltage
• 1.26-V Core Supply Voltage
Applications of TMS320VC5501PGF300
The TMS320VC5501 (5501) fixed-point digital signal processor (DSP) is based on the TMS320C55x DSP generation CPU processor core. The C55x DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform data transfers independent of the CPU activity.
Environmental & Export Classifications of TMS320VC5501PGF300
| ATTRIBUTE | DESCRIPTION |
| RoHS Status | ROHS3 Compliant |
| Moisture Sensitivity Level (MSL) | 4 (72 Hours) |
| REACH Status | REACH Unaffected |
| ECCN | 3A991A2 |
| HTSUS | 8542.31.0001 |
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