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EPM3128ATC-10 N Integrated Circuit Chip With CPLD 128MC 10NS 100TQFP
Product Details:
| Place of Origin: | Original |
| Brand Name: | Original |
| Certification: | Original |
| Model Number: | EPM3128ATC-10 N |
Payment & Shipping Terms:
| Minimum Order Quantity: | 1 |
|---|---|
| Price: | negotiation |
| Packaging Details: | carton box |
| Delivery Time: | 3-4working days |
| Payment Terms: | T/T |
| Supply Ability: | 100 |
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Detail Information |
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| Delay Time Tpd(1) Max: | 10 Ns | Voltage Supply - Internal: | 3V ~ 3.6V |
|---|---|---|---|
| Number Of Logic Elements/Blocks: | 8 | Number Of Macrocells: | 128 |
| Number Of Gates: | 2500 | Number Of I/O: | 80 |
| High Light: | EPM3128ATC-10 N Integrated Circuit Chip,Integrated Circuit Chip 100TQFP |
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Product Description
EPM3128ATC-10 N Integrated Circuit Chip With CPLD 128MC 10NS 100TQFP
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IC CPLD 128MC 10NS 100TQFP
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Specifications of EPM3128ATC-10 N
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TYPE
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DESCRIPTION
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Category
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Integrated Circuits (ICs)
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CPLDs (Complex Programmable Logic Devices)
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Mfr
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Intel
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Series
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MAX® 3000A
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Package
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Tray
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Programmable Type
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In System Programmable
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Delay Time tpd(1) Max
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10 ns
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Voltage Supply - Internal
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3V ~ 3.6V
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Number of Logic Elements/Blocks
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8
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Number of Macrocells
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128
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Number of Gates
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2500
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Number of I/O
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80
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Operating Temperature
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0°C ~ 70°C (TA)
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Mounting Type
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Surface Mount
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Package / Case
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100-TQFP
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Supplier Device Package
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100-TQFP (14x14)
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Base Product Number
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EPM3128
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Environmental & Export Classifications of EPM3128ATC-10 N
| ATTRIBUTE | DESCRIPTION |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| REACH Status | REACH Unaffected |
| ECCN | EAR99 |
| HTSUS | 8542.39.0001 |
Features of EPM3128ATC-10 N
■ High–performance, low–cost CMOS EEPROM–based programmable logic devices (PLDs) built on a MAX® architecture (see Table 1)
■ 3.3-V in-system programmability (ISP) through the built–in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability
– ISP circuitry compliant with IEEE Std. 1532
■ Built–in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990
■ Enhanced ISP features:
– Enhanced ISP algorithm for faster programming
– ISP_Done bit to ensure complete programming
– Pull-up resistor on I/O pins during in–system programming
■ High–density PLDs ranging from 600 to 10,000 usable gates
■ 4.5–ns pin–to–pin logic delays with counter frequencies of up to 227.3 MHz
■ MultiVoltTM I/O interface enabling the device core to run at 3.3 V, while I/O pins are compatible with 5.0–V, 3.3–V, and 2.5–V logic levels
■ Pin counts ranging from 44 to 256 in a variety of thin quad flat pack
(TQFP), plastic quad flat pack (PQFP), plastic J–lead chip carrier (PLCC), and FineLine BGATM packages
■ Hot–socketing support
■ Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance
■ 3.3-V in-system programmability (ISP) through the built–in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability
– ISP circuitry compliant with IEEE Std. 1532
■ Built–in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990
■ Enhanced ISP features:
– Enhanced ISP algorithm for faster programming
– ISP_Done bit to ensure complete programming
– Pull-up resistor on I/O pins during in–system programming
■ High–density PLDs ranging from 600 to 10,000 usable gates
■ 4.5–ns pin–to–pin logic delays with counter frequencies of up to 227.3 MHz
■ MultiVoltTM I/O interface enabling the device core to run at 3.3 V, while I/O pins are compatible with 5.0–V, 3.3–V, and 2.5–V logic levels
■ Pin counts ranging from 44 to 256 in a variety of thin quad flat pack
(TQFP), plastic quad flat pack (PQFP), plastic J–lead chip carrier (PLCC), and FineLine BGATM packages
■ Hot–socketing support
■ Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance
■ PCI compatible
■ Bus–friendly architecture including programmable slew–rate control
■ Open–drain output option
■ Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls
■ Programmable power–saving mode for a power reduction of over 50% in each macrocell
■ Configurable expander product–term distribution, allowing up to 32 product terms per macrocell
■ Programmable security bit for protection of proprietary designs
■ Enhanced architectural features, including:
– 6 or 10 pin– or logic–driven output enable signals
– Two global clock signals with optional inversion
– Enhanced interconnect resources for improved routability
– Programmable output slew–rate control
■ Software design support and automatic place–and–route provided by Altera’s development systems for Windows–based PCs and Sun
SPARCstations, and HP 9000 Series 700/800 workstations
■ Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from third–party manufacturers such as Cadence, Exemplar Logic, Mentor
Graphics, OrCAD, Synopsys, Synplicity, and VeriBest
■ Programming support with the Altera master programming unit (MPU), MasterBlasterTM communications cable, ByteBlasterMVTM
parallel port download cable, BitBlasterTM serial download cable as well as programming hardware from third–party manufacturers and
any in–circuit tester that supports JamTM Standard Test and Programming Language (STAPL) Files (.jam), Jam STAPL Byte-Code
Files (.jbc), or Serial Vector Format Files (.svf)
■ Bus–friendly architecture including programmable slew–rate control
■ Open–drain output option
■ Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls
■ Programmable power–saving mode for a power reduction of over 50% in each macrocell
■ Configurable expander product–term distribution, allowing up to 32 product terms per macrocell
■ Programmable security bit for protection of proprietary designs
■ Enhanced architectural features, including:
– 6 or 10 pin– or logic–driven output enable signals
– Two global clock signals with optional inversion
– Enhanced interconnect resources for improved routability
– Programmable output slew–rate control
■ Software design support and automatic place–and–route provided by Altera’s development systems for Windows–based PCs and Sun
SPARCstations, and HP 9000 Series 700/800 workstations
■ Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from third–party manufacturers such as Cadence, Exemplar Logic, Mentor
Graphics, OrCAD, Synopsys, Synplicity, and VeriBest
■ Programming support with the Altera master programming unit (MPU), MasterBlasterTM communications cable, ByteBlasterMVTM
parallel port download cable, BitBlasterTM serial download cable as well as programming hardware from third–party manufacturers and
any in–circuit tester that supports JamTM Standard Test and Programming Language (STAPL) Files (.jam), Jam STAPL Byte-Code
Files (.jbc), or Serial Vector Format Files (.svf)
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